This invention relates to data processing systems and more particularly to the use of semiconductor memory subsystems employing single bit error correction/double bit error detection (SBC/DBD).
Semiconductor memory subsystems using large scale integrated circuit (LSI) techniques have proven to be cost-effective for certain applications of storing digital information. Most semiconductor memory subsystems are comprised of a plurality of similar memory storage devices or bit planes each of which is organized to contain as many memory storage cells or bits as feasible in order to reduce per bit costs and to also contain addressing and read and write circuits in order to minimize the number of connections to each memory storage device. In many designs, this has resulted in an optimum memory storage device or bit plane that is organized as 2.sup.W words of one bit each, typically 256, 1024 or 4096. Certain contemporary technologies produce memory storage devices of 2.sup.14 or more bits. Because of the one bit organization of the memory storage device, single bit error correction as described by Hamming in the publication "Error Detecting and Correcting Codes", R. W. Hamming, The Bell System Journal, Volume XXIX, April 1950, No. 2, pp. 147-160, has proven quite effective in correcting the error of a single memory storage device or bit in a given word, i.e., a single bit error, the word being of a size equal to the word capacity of the semiconductor memory subsystem, without causing loss of data readout from the semiconductor memory subsystem.
Because the memory storage devices are quite complex, and because many are used in a semiconductor memory subsystem, they usually represent the predominate component failure in a semiconductor memory subsystem. Consequently, it is common practice to employ some form of single bit error correction along the line described in Hamming. While single bit error correction allows for tolerance of single bit memory storage cell failure, as more malfunctions occur, the statistical chance of finding two of them, i.e., a double bit error, in the same word increases. While the method to accomplish double bit error correction as suggested by Hamming has been known in the art for some time, the cost of the additional circuitry required has made the technique economically unfeasible for most commercial applications. Recent work in the art has taught methods for the logging of errors for scheduling maintenance before the occurrence of a double bit error as disclosed by Petschauer in U.S. Pat. No. 3,999,051.
The present invention addresses the double bit error problem by providing a technique for correcting double bit errors by improvements to the existing SBC/DBD technology.